Continuous-bits provides algorithm development and implementation
in software and as FPGA and ASIC IP-cores
for signal-processing, machine-learning, and neural-networks
Custom IP-cores:
If you look for an FPGA and ASIC/FPGA IP-core to do your signal processing...
If the core seems complex and challenging, and no similar IP is available on the market...
We, at Continuous-bits, can help you!
We have the knowledge and experience both in signal processing and in logic design, and the ability to provide you with the IP-core you need.
The HDL code is delivered with test-bench environment, C, Python, Octave, and Matlab simulations.
Contact us with a short description of the needed IP-core.
Forward error correction IP-cores:
Our of-the-shelf products includes forward error correction RTL implementation of LDPC and Turbo codes. Our architecture is flexible and allow us to add special features and combination of standards per-customer request. Our IP-cores usually support a combination of several LDPC standards and combination of LDPC and Turbo standards.
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Verification IPs:
Our verification IPs, are tailored to you specific project needs, and address the needs of signal-processing RTL implementation.
RTL architecture verification
The Python/Octave/Matlab/Cpp algorithm simulation, is modified according to the RTL architecture, to verify the performance of the architecture.
This is an iterative process, that affects the architecture, from simple decisions, like buffer size and fixed-point conversion,
to more complex decisions as HW/SW partition, process scheduling and resource allocations.
RTL implementation verification
Verification environments, both at the module level and at the full chip level.